The need for higher speed circuitries in circuitized substrates such as those used in multilayered printed circuit boards (PCBs), chip carriers, etc. have arisen due to technological advances, in turn giving rise to the need for higher speed digital signal transmissions. If not properly implemented, the reduction in the rise and fall time of high-frequency digital signals propagating within the final product, e.g., a PCB, may lead to a compromise in signal integrity, for example cross-talk noise and signal distortions due to impedance mismatch.
A signal path of a PCB or chip carrier at relatively low frequencies may be represented electrically as a lumped network of series resistances and shunt capacitances. However, as the frequency (speed) is increased, this approach of lumped circuit modeling breaks down, and signal paths must be regarded as transmission lines. The common transmission line structures used, for example, in PCBs, are microstrip, embedded microstrip, stripline and dual striplines. The microstrip configuration simply refers to the case where the conductor is separated from a reference plane, either ground or power, by a dielectric. The stripline configuration, on the other hand, has reference planes above and below the conductor. A typical multilayer PCB of more than two signal layers may have both stripline and microstrip geometries.
The present invention as defined herein is directed at reducing and substantially eliminating cross-talk noise between transmission lines located on conductive layers in a circuitized substrate as well as, significantly, interconnecting conductive thru-holes, such as used in a multilayered PCB or chip carrier by providing effective shielding of the lines and thru-holes. Crosstalk, as is known, is a category of noise induced primarily by the electromagnetic coupling between lines. In multilayered PCBs, especially those of relatively complex construction, crosstalk can occur by the electrical coupling between relatively closely spaced signal traces (lines). Crosstalk decreases noise margins and degrades signal quality. This, of course, can be a major limiting factor in communication systems performance. Crosstalk increases with longer trace coupling distances, smaller separation between traces, shorter pulse rise and fall times, larger magnitude currents or voltages being switched.
Inductive and capacitive coupling are the two known types of signal coupling that are the crosstalk determinant in a multilayered PCB circuit plane. These two types of coupling decrease with increasing distance between source and receiver. Most crosstalk can be attributed to adjacent wires. Because parallel and adjacent wires on a PCB conductive layer interact both capacitively and inductively, the distance over which adjacent wires are parallel needs to be carefully controlled. To minimize crosstalk, some high frequency designs incorporate ground planes under each signal layer, which have proven to virtually eliminate the crosstalk between these layers. Ideally, then, crosstalk between neighboring signals can be reduced by maximizing signal-to-signal spacing and by minimizing signal-to-ground distances. These factors, plus a host of others, contain many interdependencies and are often at odds with one another. For example, high wiring density is required to minimize interconnect delays as well as size, cost and weight. However, as lines are placed closer together, their mutual coupling increases, with a corresponding rise in crosstalk levels.
The design of PCBs, chip carriers and similar structures which include circuitized substructures (e.g., those often referred to as “cores”) as part thereof, therefore, has become quite a challenging task, especially when designing high-performance and high-density final products. Most significantly, electromagnetic coupling between the adjacent signal lines (aka traces) is one factor that sets the upper limit to the interconnect density.
In one known multilayered PCB structure, the structure includes a first layer having an electrically conductive plane for electrical connection to a common armature contact of a relay, the electrically conductive plane being sized to substantially cover a mounting footprint of the relay. This PCB structure also includes a second layer parallel to and electrically separate from the first layer, the second layer having an electrically conducting first section for electrical connection to a normally-open contact of the relay and an electrically conducting second section for electrical connection to a normally-closed contact of the relay. The first and said second sections are electrically separate from each other and, in combination with each other, are planar and sized to substantially cover the mounting footprint of the relay.
In U.S. Pat. No. 6,713,685, there is described a method of cutting away material in a PCB so as to form non-circular vias. Laser or plasma ablation is used to remove PCB material about a centerline. This type of material removal allegedly allows lateral movement to create the non-circular patterns. The described resulting shapes for the vias may be circular, square, extended (elongated) and trench-shaped. The trench vias may be micro milled to form a coaxial structure that provides noise suppression and EMI protection, and may be elongated to be much larger than the diameter of a circular micro-via.
In U.S. Pat. No. 6,529,229, first and second clock signal lines are preferably mutually adjacent, and preferably weave around electrode pads and/or wiring patterns used to interconnect the driver ICs. The preferred even-odd variation of the interconnections between the driver integrated circuits (ICs) and the clock signal lines facilitates the mutually adjacent weaving layout of the clock signal lines, which improves their noise immunity. The clock signal lines preferably include in-line electrode pads to which the clock input terminals of the driver ICs are coupled. The in-line electrode pads reduce reflection of the clock signals because they avoid characteristic-impedance discontinuities.
In U.S. Pat. No. 6,444,922, there is described eliminating crosstalk between copper signal lines in a PCB in which a metal shield is formed around each signal trace from the transmit end to the receive end. The metal shield is built from a microstrip or stripline in the PCB by cutting grooves from the surface on both sides of the signal line, through the dielectric material to the underlying ground plane, thereby exposing the ground metal all along the bottom of the channel. The grooves are formed using techniques adapted from microvia technology. Metallization is then applied to the top surface and the grooves (side walls and bottom) resulting in the formation of a complete metal shield around the signal line comparable to that of a coaxial cable. The metal shield isolates the signal from radiating any energy or interference to neighboring signal lines.
In U.S. Pat. No. 5,057,798, there is described the forming of an RF (radio frequency) line on the front and back sides of a ceramic hybrid circuit board containing other components. The RF line is formed on the top side of the circuit board to facilitate connections to other circuit boards and/or RF components, but is routed underneath the board to traverse the areas of the board occupied by other components. When the RF line is on the top side of the substrate, the ground plane is established by the metal layer on the bottom of the substrate; and when the RF line is on the bottom of the substrate, the ground plane is established with the metal layer on top of the substrate. The connection from the topside and backside RF lines is accomplished by low VSWR plated via holes through the substrate. The patent mentions that the grounding mechanisms add matching shunt capacitance, a ground from nearby via openings forms a “quasi coaxial structure” and microstrip line end fringing is possible as a tuning feature.
Coupling semiconductor devices (integrated circuits or chips), including those of the multi-mode variety (analog and digital) onto PCBs, has resulted in various attempts to reduce noise generation and the associated problems. One attempt to solve the noise problem involves the addition of decoupling capacitors placed near the active devices. The decoupling capacitors stabilize the current flowing to these devices. However, while the capacitor absorbs some of the voltage, an undesirable spike still occurs.
Another known attempt to manage switching noise in multi- or mixed-mode structures involves partitioning analog and digital functions. This process requires unique manufacturing processes and custom designs. For example, U.S. Pat. No. 6,020,614 suggests that noise can be reduced by establishing boundary zones between the analog and digital circuits of a semiconductor substrate with the analog circuit having a separate power supply bus from the digital circuit. Further, this patent mentions providing interconnect signal lines such that the isolated wires between the circuits may functionally interact with other circuits while the substrate noise coupling from other circuits remains low. However, spacing the analog components from the digital components can waste precious semiconductor space, which is an important consideration in integrated circuit (and PCB) design.
Yet another attempt to resolve switching noise problems in a multi-mode structure is addressed in U.S. Pat. No. 5,649,160. This patent suggests that the noise can be reduced by shaping the noise from the digital circuit and concentrating it in a single or a small number of parts of the frequency spectrum. This solution relies on the concept that the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference.
Other approaches for arranging transmission lines on microwave circuit structures are described in U.S. Pat. Nos. 6,429,752, 6,429,757 and 6,522,214. And, in U.S. Pat. No. 5,031,073, there is described a PCB in which the board's circuitry is partitioned into a plurality of circuit regions which are selectively isolated with respect to input and output signals. Signal lines in one region are arranged in a closely spaced array aligned with, but spaced from, a corresponding array in an adjacent region. Other shielding structures are described in U.S. Pat. Nos. 5,196,230, 5,684,340 and 6,040,524.
Additional examples of various PCB multilayered structures are shown and described in U.S. Pat. Nos. 6,495,772, 6,518,516 and 6,832,436, in addition to U.S. Published Application US2004/0009666 A1, the teachings of which are incorporated herein by reference, as are the teachings of the other documents cited in this Background.
As defined hereinbelow, the present invention defines a circuitized substrate in which signal conductors adapted for passing high frequency signals are shielded by solid shield members strategically positioned within the substrate's dielectric member relative to the signal conductors. The shield members may be parallel and perpendicular to the signal conductors and may also be of cylindrical configuration to surround the conductive thru-hole(s) which also forms part of the invention. A method of forming the substrate, as well as electrical assemblies and information handling systems using same are also provided. It is believed that such an invention will represent a significant advancement in the art.